The hybrid integration of IC and MEMS technology was dominated during the past decades by two-dimensional side-by-side approaches for Multi Chip Modules (MCM) and Systems on Chips (SoC). CMOS and MEMS processing are both well-established and cost-effective base technologies where each technology itself is typically characterized by short development times, low fabrication costs and high yields. The separate manufacturing of CMOS and MEMS and the integration of both devices as a final step in packaging is, in terms of process costs and versatility, an attractive alternative to Systems on Chips, where these two technologies are laborious merged onto a common die. The trend in many integration concepts moves therefore clearly towards three-dimensional integrated System in Packages (SiP). This vertical integration by chip stacking does not only decrease the costs by reducing the package size, its volume and weight, but also improves the systems performance in terms of enhanced transmission speed, lower power consumption, and lower parasitic capacitances due to shorter signal lengths, which is of importance for various demanding applications. These integration concepts require vertical interconnects which lead through certain chips/substrates/carriers of the stack in order to connect its functional layers. Large developing efforts for the realization of reliable and cost-effective Through-Silicon Vias (TSV's) are currently on-going and first commercial products have already successfully incorporated this technology.
The structure and thus the fabrication of TSV's can be roughly divided into three major elements as being illustrated in FIG. 1, which illustrates, in a cross-sectional view, a component 107 comprising a substrate, chip, or carrier 104 of insulating or semiconducting material, for example silicon, glass ceramic or others, with a plurality of TSV's: through holes 101 going through the substrate 104, an electrically conductive core 102 comprising metallic or semi-metallic conductive via material, and a dielectric material 103 acting as an insulator between the electrically conductive core 102 and the substrate 104. Each TSV forms a vertical electrical interconnection between the front and back sides of the substrate 104. As an example, each TSV connect to a redistribution layer 105 on one side of the substrate for connection to integrated circuits or associated devices, optical or optoelectronic elements, micromechanical or micro-electromechanical elements, additional wiring, etc., which are disposed in the layer 105; and to solder bumps 106 on an opposite side of the substrate 104 for connection to next level. The actual design of the TSV's depends very much on the application and its demands.
The most popular process techniques for the fabrication of the TSV's are in the following briefly discussed:
Various methods for the formation of via holes exist and can be categorized into dry etching, wet etching, and drilling processes. All processes have their own characteristics and thus result in different physical properties of the via holes. The diameter of the via holes depends strongly on the application and varies typically between 1 μm and 1200 μm. Vertically straight sidewalls are typically fabricated for solid metal-filled TSV's with small diameters, whereas tapered sidewall profiles are used for metal-lined TSV's with rather larger diameters.
The predominantly used processes for the via hole formation so far are Deep Reactive Ion Etching (DRIE), Water Jet Drilling, Sand Blasting, and Laser Ablation. DRIE is by far the most commonly used technology to form the via holes due to its excellent process controllability and its capability to create high aspect ratio vias and various profiles of the sidewalls. Using Laser Ablation to drill the via holes benefits from the absence of any lithographic process steps and the non-selectivity towards different material stacks. This allows a very flexible processing and fast incorporation of design changes. However this method suffers from a high local thermal load creating pores and micro-cracks and a dust particle generation and a deformation concentrically to the drilled via holes, which may lead to reliability issues. Methods like micro drilling, powder blasting, cryogenic etching, wet etching techniques such as photo-electrochemical etching have also been reported but are not broadly applied yet. Traditional substrate thicknesses are in the range of 0.01 mm to 3 mm with through via aspect ratios in the range of 1:1 to 30:1. The dimensions depend strongly on the application and I/O count.
The metallization step is the most critical and costly part of the via fabrication. Especially the electroplating of copper as a very well established semiconductor process is widely used in most research groups within industry and university to form the conducting path. The process benefits from its good availability and processability of high aspect ratio features at close to room temperature conditions but is however not yet economically attractive due to its complexity. Especially the void-free metal formation of high aspect ratio features is a big challenge. The cost target of currently applied TSV processes is about 200 USD per 200 mm wafer. A major part in this cost structure is the metal filling with about 20-30% of the total costs. Alternative approaches to plating processes are therefore investigated, such as the filling of the via holes with conducive metal pastes, the use of polysilicon or low resistivity silicon as conductor.
Filling of high aspect ratio vias, with a height in the range of 10 μm to 100 μm and a diameter in the range of 1 μm to several hundred μm's is challenging. A popular technique for filling blind vias or through vias of microscale diameters is electroplating of cupper. However, the hydrodynamics, the ionic concentrations, and the diffusivities limit the filling of deep blind holes.
Chemical Vapour Deposition (CVD) of silicon dioxide is a well-established CMOS process and therefore often used for forming the insulator surrounding the conductor because of its moderate temperature conditions. Organic dielectrics such as benzocyclobutene (BCB), SU8, or parylene are also used. The polymers are typically applied by conventional spin-on or parylene deposition processes as well as by spray coating. Most of the TSV concepts use a very thin insulating layer in order to minimize the via diameter and pitch.